The present invention relates to a semiconductor device designed using a standard cell methodology, and more particularly relates to a layout structure which allows independent supply of a substrate potential and a power supply potential of a standard cell and a design method therefor.
With increase in the degree of integration and size of LSIs (semiconductor integrated circuits), which are a kind of semiconductor device, a standard cell methodology has been generally used as a design method for LSIs. Meanwhile, performance demands for LSIs have been increased and, furthermore, reduction in power consumption has been strongly required.
As a technique for reducing power consumption in an LSI employing a CMOSFET (complementary metal-oxide-semiconductor field-effect transistor), there has been a known technique in which a substrate potential of a MOSFET is controlled separately from a power source potential of the MOSFET to change a threshold voltage, thereby reducing an off leakage current of the MOSFET according to an operation state of the LSI. To use this technique, it is necessary that a substrate potential and a power supply potential of a MOSFET can be set to be different values, respectively. That is, the LSI has to have a layout structure in which a substrate potential supply source and a power supply potential supply source have to be separately located.
To implement the layout structure including a substrate potential supply line and a power supply potential supply line separately provided in an LSI designed by using a standard cell methodology, a layout structure including cells and cell rows arranged in the following manner has to be formed. A substrate potential supply line and a power supply potential supply line are formed so as to be electrically separated in a lower interconnect layer in each standard cell, using some means, substrate potential supply lines of a plurality of standard cells are connected to one another and power supply potential supply lines of the plurality of standard cells are connected to one another, and then the substrate potential supply lines and the power supply potential supply lines are connected to main power supply lines from an upper layer with the substrate potential supply lines electrically separated from the power supply potential supply lines (hereinafter, this layout structure will be called strap interconnection).
Hereinafter, two examples of known techniques for separating a substrate potential supply source and a power supply potential supply source will be described.
<<First Known Technique>>
FIG. 29 is a plan view of a standard cell 300 in a semiconductor device according to a first known technique. FIG. 30 is a cross-sectional view taken along the line A-B shown in FIG. 29.
The standard cell 300 of FIG. 29 includes a p-type MOSFET formation region 111 and an n-type MOSFET formation region 211. In the p-type MOSFET formation region 111, an impurity doped region 105 of a p-type MOSFET is connected to a first metal interconnect 107 through a contact hole 106. The first metal interconnect 107 supplies a high level power supply potential (VDD) to the impurity doped region 105 of the p-type MOSFET. In the n-type MOSFET formation region 211, an impurity doped region 205 of the n-type MOSFET is connected to a first metal interconnect 207 (in the same layer as the first metal interconnect 107) through a contact hole 206. The first metal interconnect 207 supplies a low level power supply potential (VSS) to the impurity doped region 205 of the n-type MOSFET. The reference numeral 303 denotes a polysilicon interconnect for formation and connection of gate electrodes of the MOSFETS.
At the outside of the first metal interconnect 107 of the p-type MOSFET formation region 111, an impurity doped interconnect 100 is connected to a first metal interconnect 102 (in the same layer as the first metal interconnect 107) through a contact hole 101. The first metal interconnect 102 receives a supply of a high level substrate potential (VDDBB: back bias) electrically separated from VDD. That is, the impurity doped region interconnect 100, the contact hole 101 and the first metal interconnect 102 together form a substrate contact region 110 of the p-type MOSFET. At the outside of the first metal interconnect 207 of the n-type MOSFET formation region 211, an impurity doped interconnect 200 is connected to a first metal interconnect 202 (in the same layer as the first metal interconnect 107) through a contact hole 201. The first metal interconnect 202 receives a supply of a low level substrate potential (VSSBB: back bias) electrically separated from VSS. That is, the impurity doped interconnect 200, the contact hole 201 and the first metal interconnect 202 together form a substrate contact region 210 of the n-type MOSFET.
FIG. 31 is a plan view illustrating known cell rows employing the standard cell 300 of FIG. 29. FIG. 31 illustrates a layout in which a plurality of standard cells 300 are arranged so as to extend in the left-right direction to form a single cell row and a plurality of cell rows are arranged in the top-down direction.
As shown in FIG. 31, each of the power supply potential supply lines 107 and 207 and the substrate potential supply lines 102 and 202 is formed around a cell boundary in a first metal interconnect layer so that a strap interconnection from main power supply lines (not shown) extending in the up-down direction can be achieved. Adjacent cell rows in the up-down direction share the substrate potential supply line 102 for receiving a supply of VDDBB. Japanese Laid-Open Publication No. 2001-230376 is an example of application of the known technique shown in FIG. 29 through FIG. 31.
<<Second Known Technique>>
FIG. 32 is a plan view illustrating a standard cell 300 and a substrate potential supply cell 301 in a semiconductor device according to a second known technique. FIG. 33 is a cross-sectional view taken along the line A-B shown in FIG. 32. FIG. 34 is a cross-sectional view taken along the line C-D shown in FIG. 32.
In the standard cell 300 of FIG. 32, a first metal interconnect 107 for receiving a supply of VDD extends to reach a cell boundary and an impurity doped interconnect 100 for receiving a supply of VDDBB is located under the first metal interconnect 107. In the same manner, a first metal interconnect 207 for receiving a supply of VSS substrate potential supply line extends to reach a cell boundary and an impurity doped interconnect 200 for receiving a supply of VSSBB is located under the first metal interconnect 207. In the substrate potential supply cell 301, the impurity doped interconnect 100 for receiving a supply of VDDBB is connected to a first metal interconnect 102 through a contact hole 101 and the impurity doped interconnect 200 for receiving a supply of VSSBB is connected to a first metal interconnect 202 through a contact hole 201.
FIG. 35 is a plan view illustrating cell rows employing the standard cell 300 and substrate potential supply cell 301 of FIG. 32. Through a strap interconnection (not shown), VDD, VSS, VDDBB and VSSBB are supplied from main power supply lines (not shown) to the first metal interconnects 107, 207, 102 and 202, respectively. Adjacent cell rows in the up-down direction share the power supply potential supply line 107 for receiving a supply of VDD. Japanese Laid-Open Publication No. 2003-309178 is an example of application of the known technique shown in FIGS. 32 through 35.
In the first known technique, a large interconnect region is required because adjacent cell rows in the up-down direction can share the substrate potential supply line 102 but not the power supply potential supply line 107. As a result, interconnect resources for signal lines connecting the standard cells 300 are reduced and the area of an LSI is increased. In contrast, to reduce the area of an interconnect region, the width of the power supply potential supply line 107 has to be reduced, and the amount of a drop in power supply from main power supply lines to the standard cells 300 is increased. This results in reduction in operation speed of the LSI.
In the second known technique, the constraint that in addition to the standard cells 300, the substrate potential supply cells 301 has to be provided in advance in a predetermined location before providing the standard cells 300 arises, and thus the degree of design freedom in forming cell rows is reduced. Moreover, an empty region in which the standard cells 300 do not exist is generated in the vicinity of the substrate potential supply cells 301. That is, a wasted area is generated in the LSI.